| Item |
Yes |
No |
Notes |
| PCB outline and dimensions match requirements |
|
|
|
| Board stack-up defined and correct |
|
|
|
| Component placement follows design rules |
|
|
|
| Clearances (trace, pad, via) verified |
|
|
|
| Power/GND planes continuity checked |
|
|
|
| Signal routing follows best practices |
|
|
|
| High-speed/critical nets checked (length, impedance) |
|
|
|
| Decoupling capacitors near IC power pins |
|
|
|
| Test points and debugging pads included |
|
|
|
| Silkscreen clarity and no over pad/holes |
|
|
|
| All reference designators visible |
|
|
|
| DRC (Design Rule Check) passed |
|
|
|
| ERC (Electrical Rule Check) passed |
|
|
|
| Gerber files generated and reviewed |
|
|
|